HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 830
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 25 LCD Controller
Bit 8—Byte Data Pixel Alignment (PABD): Sets the pixel data alignment type in one byte of
data. The contents of aligned data per pixel are the same regardless of this bit's setting. For
example, data H'05 should be expressed as 0101 (binary) which is the normal style handled by a
MOV instruction of the SH7727 CPU, and should not be selected between 0101 (binary) and 1010
(binary).
Bit 8
PABD
0
1
Bits 6 to 0—Display Color Select (DSPCOLOR6 to DSPCOLOR0): Set the number of display
colors for the display (0 is written to upper bits of for unpacked 4, 5, and 6 bpp). For display
colors to which the description (via palette) is added below, the color set by the color palette is
actually selected by the display data and displayed.
Bit 6
DSP
COLOR6
0
Other than above
Note: The number of colors that can be selected in rotation mode is restricted by the display
Rev.6.00 Mar. 27, 2009 Page 772 of 1036
REJ09B0254-0600
resolution. For details, see table 25.3, in section 25.3, Operation.
Bit 5
DSP
COLOR5
0
1
Description
Big endian for byte data
Little endian for byte data
Bit 4
DSP
COLOR4
0
1
0
Bit 3
DSP
COLOR3
0
1
1
1
Bit 2
DSP
COLOR2
0
0
1
0
1
1
1
Bit 1
DSP
COLOR1
0
1
0
1
0
0
0
Bit 0
DSP
COLOR0 Description
0
1
0
0
0
0
1
1
Monochrome, 2 grayscales,
1 bpp (via palette)
Monochrome, 4 grayscales,
2 bpp (via palette)
Monochrome, 16 grayscales,
4 bpp (via palette)
Monochrome, 64 grayscales,
6 bpp (via palette)
Color, 16 colors, 4 bpp (via
palette)
Color, 256 colors, 8 bpp (via
palette)
Color, 32k colors (RGB: 555),
15 bpp
Color, 64k colors (RGB: 565),
16 bpp
Reserved
(Initial value)
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