HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 81

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode and
2. Bank register
3. Bank register
4. Bank register
31
indexed GBR indirect addressing mode.
Accessed as a general register when the RB bit is set to 1 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is cleared to 0.
Accessed as a general register when the RB bit is cleared to 0 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is set to 1.
(a) User mode register
Figure 2.1 Register Configuration in Each Processing Mode (1)
configuration
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
MACH
MACL
GBR
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
*1 *2
*2
*2
*2
*2
*2
*2
*2
0
(b) Privileged mode register
31
configuration (RB = 1)
R0_BANK1
R0_BANK0
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
MACH
MACL
GBR
SSR
VBR
SPC
R10
R12
R13
R14
R15
R11
SR
PR
PC
R8
R9
*1 *3
*1 *4
*3
*3
*3
*3
*3
*3
*3
*4
*4
*4
*4
*4
*4
*4
Rev.6.00 Mar. 27, 2009 Page 23 of 1036
0
31
(c) Privileged mode register
configuration (RB = 0)
R0_BANK0
R0_BANK1
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
MACH
MACL
SSR
GBR
VBR
SPC
R10
R12
R13
R14
R15
R11
SR
PR
PC
R8
R9
*1 *4
*1 *3
*4
*4
*4
*4
*4
*4
*4
*3
*3
*3
*3
*3
*3
*3
REJ09B0254-0600
Section 2 CPU
0