HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 781
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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23.9.4
The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must
be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations.
23.9.5
The endpoint 1 data register (EPDR1) cannot be cleared when DMA transfer for endpoint 1 is
enabled (EP1 DMAE in USBDMA = 1). Cancel DMA transfer before clearing the register.
23.9.6
Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i,
EP2, or EP3.
The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent
from the USB host. However, at the timing shown in figure 23.15, multiple TR interrupts occur
successively. Take appropriate measures against malfunction in such a case.
Note: This module determines whether to return NAK if the FIFO of the target EP has no data
CPU
Host
USB
when receiving the IN token, but the TR interrupt flag is set only after a NAK handshake
is sent. If the next IN token is sent before PKTE of TRG is written to, the TR interrupt flag
is set again.
Assigning Interrupt Sources to EP0
Clearing the FIFO when DMA Transfer Is Enabled
Notes on TR Interrupt
IN token
Determines whether
to return NAK
NAK
Figure 23.15 TR Interrupt Flag Set Timing
Sets TR flag
TR interrupt routine
Clear
TR flag
IN token
Determines whether
to return NAK
Writes
transmit data
Rev.6.00 Mar. 27, 2009 Page 723 of 1036
NAK
Section 23 USB Function Controller
Sets TR flag
(Sets the flag again)
TRG.
PKTE
TR interrupt routine
REJ09B0254-0600
IN token
Transmits data
ACK
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