HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 578

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 17 Serial Communication Interface (SCI)
In receiving, the SCI operates as follows:
1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes
2. Receive data is shifted into the SCRSR in order from the LSB to the MSB.
3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following
Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1.
4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
Table 17.12 Receive Error Conditions and SCI Operation
Receive Error
Overrun error
Framing error
Parity error
Figure 17.11 shows an example of SCI receive operation in the asynchronous mode.
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REJ09B0254-0600
internally and starts receiving.
checks:
a. Parity check: The number of 1s in the receive data must match the even or odd parity
b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit
c. Status check: RDRF must be 0 so that receive data can be loaded from the SCRSR into the
If these checks all pass, the SCI sets RDRF to 1 and stores the received data in the SCRDR. If
one of the checks fails (receive error), the SCI operates as indicated in table 17.12.
SCSCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER,
PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCSCR is
also set to 1, the SCI requests a receive-error interrupt (ERI).
setting of the O/E bit in the SCSMR.
is checked.
SCRDR.
Be sure to clear the error flags.
Abbreviation
ORER
FER
PER
Condition
Receiving of next data ends while
RDRF is still set to 1 in SCSSR
Stop bit is 0
Parity of receive data differs from
even/odd parity setting in SCSMR
Data Transfer
Receive data not loaded
from SCRSR into SCRDR
Receive data loaded from
SCRSR into SCRDR
Receive data loaded from
SCRSR into SCRDR