HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 816

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 24 USB HOST Module
Data is filled from the lower bits of the memory in writing so that the data is read/written in bi-
direction consistently regardless of the endian type. That is, the data is always aligned with the
little endian specification.
24.3.2
ED (endpoint descriptor) and TD (transfer descriptor) that define each transfer transaction of USB
Host Controller must be aligned so that each Dword corresponds to the long-word boundary
(addresses 4n to 4n + 3) of the memory.
24.4
24.4.1
The transferred data is stored in shared system memory with CPU. The data alignment in system
memory are restricted depends on synchronous DRAM specification which is used as system
memory.
In above figure, transfer data 1 and 3 are able to be read or written by USB Host Controller. But
transfer data 2 are possibly unable to be read or written by USB Host controller. Any data which
have possibility to be accessed by USB Host Controller must be aligned in synchronous DRAM
not to cross row address alignment.
Rev.6.00 Mar. 27, 2009 Page 758 of 1036
REJ09B0254-0600
Storage Format of the Descriptor
Data Alignment Restriction of USB Host Controller
Restriction on the Line Boundary of the Synchronous DRAM
DRAM
Row address
Row address
Row address
n
n+1
n+2
Memory area
(2)
(3)
(1)