HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 612

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 18 Smart Card Interface
Table 18.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode)
P
7.1424
10.00
10.7136
13.00
14.2848
16.00
18.00
The bit rate error is found as follows:
Table 18.8 shows the relationship between transmit/receive clock register set values and output
states on the smart card interface.
Table 18.8 Register Set Values and SCK0 Pin
Setting
1 *
2 *
3 *
Notes: 1. The SCK0 output state changes as soon as the CKE0 bit is modified. The CKE1 bit
Rev.6.00 Mar. 27, 2009 Page 554 of 1036
REJ09B0254-0600
φ
1
2
2
(MHz)
2. The clock duty remains constant despite stopping and starting of the clock by
Error (%) = (
should be cleared to 0.
modification of the CKE0 bit.
SMIF
1
1
1
1
1
1
C/A
0
0
1
1
1
1
1488 × 2
Register Value
Maximum Bit Rate (Bit/s)
9600
13441
14400
17473
19200
21505
24194
2n−1
CKE1
0
0
0
0
1
1
Pφ
× B × (N + 1)
CKE0
0
1
0
1
0
1
× 10
Output
Port
Low output
High output
6
− 1) × 100
State
Determined by setting of port
register SCP1MD1 and
SCP1MD0 bits
SCK0 (serial clock) output state
Low output state
SCK0 (serial clock) output state
High output state
SCK0 (serial clock) output state
SCK0 Pin
0
0
0
0
0
0
0
N
0
0
0
0
0
0
0
n