HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 544

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 17 Serial Communication Interface (SCI)
17.1.4
Table 17.2 summarizes the SCI internal registers. These registers select the communication mode
(asynchronous or clock synchronous), specify the data format and bit rate, and control the
transmitter and receiver sections.
Table 17.2 Registers
Name
Serial mode register
Bit rate register
Serial control register
Transmit data register
Serial status register
Receive data register
Port SC data register
Port SC control register
Notes: Registers with addresses beginning at H'04 are located in area 1 of physical space.
Rev.6.00 Mar. 27, 2009 Page 486 of 1036
REJ09B0254-0600
Consequently, when the cache is on, either access these registers from the P2 area of
logical space or else make an appropriate setting using the MMU so that these registers
are not cached.
1. The only value that can be written is 0 to clear the flags.
2. When address translation by the MMU is not executed, the address in parentheses
Register Configuration
should be used.
Abbreviation
SCSMR
SCBRR
SCSCR
SCTDR
SCSSR
SCRDR
SCPDR
SCPCR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W) *
R
1
Initial Value
H'00
H'FF
H'00
H'FF
H'84
H'00
H'00
H'8008
Address
H'FFFFFE80
H'FFFFFE82
H'FFFFFE84
H'FFFFFE86
H'FFFFFE88
H'FFFFFE8A
H'04000136
(H'A4000136) *
H'04000116
(H'A4000116) *
2
2
Access size
8
8
8
8
8
8
8
16