HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 499
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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14.6
1. The DMA channel control registers (CHCR0 to CHCR3) can be accessed with any data size.
2. When modifying the RS0 to RS3 bits in CHCR0 to CHCR3, first clear the DE bit to 0 (when
3. If an NMI interrupt is input when the DMAC is not operating, the NMIF bit of the DMAOR is
4. A transition to standby mode should be made after the DME bit in DMAOR is cleared to 0 and
5. The on-chip supporting modules that the DMAC can access are, SIOF, SCIF, USBF, A/D
6. When starting up the DMAC, set CHCR or DMAOR last. Specifying other registers last does
7. When the DMA transfer ends normally and subsequently the maximum number of transfers is
8. When using the address reload function, specify the burst mode for the transfer mode. In the
9. When using the address reload function, set a multiple of four to DMATCR. Specifying other
10. When detecting an external request at the falling edge, keep the external request pin high when
11. Do not access the space from H'4000062 to H'400006F, which is not used by the DMAC.
12. The WAIT signal is ignored when writing to an external address area using DMA 16-byte
13. Big-endian access is used when transferring data from XY memory using the DMAC if all of
The DMA operation register (DMAOR) must be accessed in byte (8 bits) or word (16 bits)
units; other registers must be accessed in word (16 bits) or longword (32 bits) units.
modifying CHCR with a byte address, be sure to set the DE bit to 0 in advance).
set.
the transfers that has been accepted by the DMAC end.
converter, D/A converter, and I/O ports. Do not access the other on-chip supporting modules
by the DMAC.
not guarantee normal operation.
performed in the same channel, write 0 to DMATCR. Otherwise, normal DMA transfer may
not be performed.
cycle-steal mode, normal DMA transfer may not be performed.
values does not guarantee normal operation.
setting the DMAC.
Accessing that space may cause malfunctions.
transfer in dual address mode, and also when transferring data from a DACK-equipped
external device to an external address area using DMA 16-byte transfer in single address
mode.
the following conditions are met:
Conditions:
(1) Transfer source address in XY memory
(2) Indirect addressing mode
(3) Byte size data
(4) Little-endian data transfer
Usage Notes
Section 14 Direct Memory Access Controller (DMAC)
Rev.6.00 Mar. 27, 2009 Page 441 of 1036
REJ09B0254-0600
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