HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 430

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 13 Li Bus State Controller (LBSC)
13.1.6
Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of
wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory
accesses. This allows direct connection of even low-speed memories without an external circuit.
WCR2 is initialized to H'FFFF by a power-on reset. It is not initialized by a manual reset or in
standby mode.
Bits 15 to 7 and 4 to 0 —Not referenced
Bits 6 and 5— Area 3 Wait Control (A3W1, A3W0): Specifies the CAS latency for the
SDRAM of area 3 of the physical space.
Bit 6: A3W1
0
1
Rev.6.00 Mar. 27, 2009 Page 372 of 1036
REJ09B0254-0600
Initial value:
Initial value:
Wait State Control Register 2 (WCR2)
R/W:
R/W:
Bit:
Bit:
Bit 5: A3W0
0
1
0
1
A6W2
A4W0
R/W
R/W
15
1
7
1
A6W1
A3W1
R/W
R/W
14
1
6
1
A6W0
A3W0
Description
SDRAM CAS Latency
1
1
2
3
R/W
R/W
13
1
5
1
A5W2
A2W1
R/W
R/W
12
1
4
1
A5W1
A2W0
R/W
R/W
11
1
3
1
A5W0
A0W2
R/W
R/W
10
1
2
1
A4W2
A0W1
R/W
R/W
1
1
9
1
(Initial value)
A4W1
A0W0
R/W
R/W
8
1
0
1