HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 694

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 20 Serial IO (SIOF)
(2) Control Data
Control data is read out/written into the following registers.
• Writing transmit control data: SITCR register (32 bit access)
• Reading receive control data: SIRCR register (32 bit access)
Figure 20.6 shows bit alignments of transmit or receive data and SITCR and SIRCR registers.
The channel number of control data is set with CD0E bit CD1E bit of SICDAR register.
Table 20.8 establishment of ch. number for control data. Use channel 0 when using only data one
channel as control data.
Table 20.8 Control Data Channel Number Establishment
Ch. Number
1
2
Rev.6.00 Mar. 27, 2009 Page 636 of 1036
REJ09B0254-0600
(a) At the control data 1ch.
(b) At the control data 2ch.
31
31
Figure 20.6 Control Data Bit Alignment
Control data ch. 0
Control data ch. 0
24 23
24 23
CD0E
1
1
16 15
16 15
Control data ch. 1
Bit
8 7
8 7
CD1E
0
1
0
0