HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 302

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 9 Power-Down Modes and Software Reset
Table 9.4
Module
Interrupt controller (INTC)
On-chip clock pulse generator
(OSC)
User break controller (UBC)
Bus state controller (BSC)
Timer unit (TMU)
Realtime clock (RTC)
A/D converter (ADC)
D/A converter (DAC)
Li bus state controller (LBSC)
LCD controller (LCDC)
USB host controller (USBH)
USB function module (USBF)
AFE interface (AFEIF)
Serial IO with FIFO (SIOF)
PC card controller (PPC)
Note: * PCC0ISR reflects the normal status.
The procedure for moving to standby mode is as follows:
1. Clear the TME bit in the WDT’s timer control register (WTCSR) to 0 to stop the WDT.
2. After the STBY bit in the STBCR register is set to 1, the SLEEP instruction is executed.
3. When the chip enters standby mode and the clocks within the chip are halted, he STATUS1
Rev.6.00 Mar. 27, 2009 Page 244 of 1036
REJ09B0254-0600
Set the WDT’s timer counter (WTCNT) to 0 and set a value to the CKS2 to CKS0 bits in the
WTCSR register to secure the specified oscillation settling time.
pin output goes low and the STATUS0 pin output goes high.
Register States in Standby Mode
Registers Initialized
—
—
—
—
TSTR register
—
All registers
—
—
—
—
—
—
—
—
Registers Retaining Data
All registers
All registers
All registers
All registers
Registers other than TSTR
All registers
—
All registers
All registers
All registers
All registers
All registers
All registers
All registers
Registers other than PCC0ISR*