HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 583

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

TXI interrupt
generated
TDRE
TEND
Serial
request
data
1
Start
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
clears TDRE bit to 0
cessing routine and
bit
0
Figure 17.14 Example of SCI Operation in Transmission
TDR with the TXI
Writes data to
interrupt pro-
D
0
D
1 frame
1
Data
D
processor
7
TXI interrupt
generated
Multi-
request
bit
0/1
Stop
bit
1
Section 17 Serial Communication Interface (SCI)
Start
bit
0
Rev.6.00 Mar. 27, 2009 Page 525 of 1036
D
0
D
1
Data
D
processor
7
Multi-
TEI interrupt
bit
0/1
generated
request
REJ09B0254-0600
Stop
bit
1
(marking)
Idling
1