HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 877
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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25.5
Note the following points when using the LCDC.
1. The following steps should be performed to prohibit access to the system memory used for
2. Notes on use of LCDC external clock
LCDC module display (synchronous DRAM in area 3).
(1) Confirm that bits LPS1 and LPS0 in the LDPMMR register are set to 1.
(2) Clear the DON bit in LDCNTR to 0 (display off mode).
(3) Confirm that bits LPS1 and LPS0 in LDPMMR are cleared to 0.
(4) Wait the display duration of one frame.
The above steps to prohibit access are necessary before entering standby mode or using the
LCDC module’s standby function.
When in clock mode 2 (crystal resonator used) and an external clock (LCLK) is used as the
LCD clock, changes in the state of the LCLK output pin can cause noise that affects the crystal
oscillator circuit, resulting in unstable PLL operation and possible malfunction.
In such a case, implement one of the following measures:
• Use an internal clock as the LCD clock when in clock mode 2.
• When using an external clock (LCLK) as the LCD clock, select a mode other than clock
mode 2 (external input on EXTAL pin).
Usage Notes
Rev.6.00 Mar. 27, 2009 Page 819 of 1036
Section 25 LCD Controller
REJ09B0254-0600
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