HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 683

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit10—Receive Control Data Ready Enable (RCRDYE)
Bit10: RCRDYE
0
1
Bit 9—Receive FIFO Full Enable (RFFULE)
Bit 9: RFFULE
0
1
Bit 8—Receive Data Transfer Request Enable (RDREQE)
Bit 8: RDREQE
0
1
Bit 4—Frame Synchronization Error Enable (FSERRE)
Bit 4: FSERRE
0
1
Bit 3—Transmit FIFO Over Run Enable (TFOVRE)
Bit 3: TFOVRE
0
1
Bit 2—Transmit FIFO Under Run Enable (TFUDRE)
Bit 2: TFUDRE
0
1
Description
Disable interrupt of receive control data ready
Enable interrupt of receive control data ready (control interrupt)
Description
Disable interrupt of receive FIFO full
Enable interrupt of receive FIFO full (control interrupt)
Description
Disable interrupt of receive data transfer request
Enable interrupt of receive data transfer request (receive interrupt)
Description
Disable interrupt of frame synchronization error
Enable interrupt of frame synchronized error (error interrupt)
Description
Disable interrupt of transmit FIFO over run
Enable interrupt of transmit FIFO over run (error interrupt)
Description
Disable interrupt of transmit FIFO under run
Enable interrupt of transmit FIFO under run (error interrupt)
Rev.6.00 Mar. 27, 2009 Page 625 of 1036
Section 20 Serial IO (SIOF)
REJ09B0254-0600
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