HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 678
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 20 Serial IO (SIOF)
20.2.8
This register shows states of SIOF. Each bit of this register becomes interrupt source when 1 is set
to corresponding register of SIIER register.
This register is initialized at power on reset or software reset.
Note: * 0 should be written into these bits. Otherwise the operation is unpredictable.
Bits 15, 11, and 7 to 5—Reserved
Bit 14—Transmit Control Data Ready (TCRDY): This bit displays condition of SITCR
register. SIOF clears when any value is written to SITCR register. This bit becomes effective
when 1 is written to TXE bit of SICTR register. SIOF issues control interrupt if interrupt issuing is
allowed for this bit. Once any data are written to SICTR register with 0 of TCRDY bit, new data is
overwritten to original data and original data of TXD_SIO will be lost.
Note: When using this bit, refer to note 2 in section 20.4, Notes on Use.
Bit 14: TCRDY
0
1
Bit 13—Transmit FIFO Empty (TFEMP): This bit is showing condition, SIOF clear by writing
to SITDR register. This bit becomes effective when 1 is written to the TXE bit of SICTR register.
SIOF issues control interrupt if interrupt issuing is allowed by this bit.
Rev.6.00 Mar. 27, 2009 Page 620 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Status Register (SISTR)
Bit:
Bit:
R*
R*
15
—
—
0
7
0
Description
Disable writing into SITCR register
Enable writing into SITCR register
TCRDY
R*
R*
14
—
0
6
0
TFEMP
R*
R*
13
—
0
5
0
TDREQ
FSERR
R/W
R*
12
0
4
0
TFOVR
R/W
R*
11
—
0
3
0
RCRDY
TFUDR
R/W
R*
10
0
2
0
RFUDR
RFFUL
R/W
R*
9
0
1
0
(Initial value)
RDREQ
RFOVR
R/W
R*
8
0
0
0
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