HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 353

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bits 8 and 7—Area 5 Burst Enable (A5BST1, A5BST0): Specify whether to use burst ROM
and PCMCIA burst mode in physical space area 5. When burst ROM and PCMCIA burst mode
are used, set the number of burst transfers.
Bit 8: A5BST1
0
1
Bits 6 and 5—Area 6 Burst Enable (A6BST1, A6BST0): Specify whether to use burst ROM
and PCMCIA burst mode in physical space area 6. When burst ROM and PCMCIA burst mode
are used, set the number of burst transfers.
Bit 6: A6BST1
0
1
Bit 7: A5BST0
0
1
0
1
Bit 5: A6BST0
0
1
0
1
Description
Access area 5 as ordinary memory
Burst access of area 5 (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
Burst access of area 5 (8 consecutive accesses).
Can be used when bus width is 8 or 16.
Burst access of area 5 (16 consecutive accesses).
Can be used only when bus width is 8.
Description
Access area 6 as ordinary memory
Burst access of area 6 (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
Burst access of area 6 (8 consecutive accesses).
Can be used when bus width is 8 or 16.
Burst access of area 6 (16 consecutive accesses).
Can be used only when bus width is 8.
Rev.6.00 Mar. 27, 2009 Page 295 of 1036
Section 12 Bus State Controller (BSC)
REJ09B0254-0600
(Initial value)
(Initial value)