HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 296

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 9 Power-Down Modes and Software Reset
Bit 6—MD5 to MD0 Pin Control (MDCHG): Specifies whether or not pins MD5 to MD0 are
switched in standby mode. When this bit is set to 1, the MD5 to MD0 pin values are latched when
returning from standby mode by means of a reset or interrupt.
Bit 6: MDCHG
0
1
Bit 5— Module Stop 8 (MSTP8): Specifies halting the clock supply to the user break controller
(UBC) in the on-chip supporting module. When the MSTP8 bit is set to 1, the clock supply to the
UBC is halted.
Bit 5: MSTP8
0
1
Bit 4—Module Stop 7 (MSTP7): Specifies halting of clock supply to the direct memory access
controller (DMAC) in the on-chip supporting module. When the MSTP7 bit is set to 1, the clock
supply to the DMAC is halted.
Bit 4: MSTP7
0
1
Bit 3—Module Stop 6 (MSTP6): Specifies halting of clock supply to the D/A converter (DAC)
in the on-chip supporting module. When the MSTP6 bit is set to 1, the clock supply to the DAC is
halted.
Bit 3: MSTP6
0
1
Bit 2—Module Stop 5 (MSTP5): Specifies halting of clock supply to the A/D converter (ADC)
in the on-chip supporting module. When the MSTP5 bit is set to 1, the clock supply to the ADC is
halted and all registers are initialized.
Rev.6.00 Mar. 27, 2009 Page 238 of 1036
REJ09B0254-0600
Description
Pins MD5 to MD0 are not switched in standby mode
Pins MD5 to MD0 are switched in standby mode
Description
UBC runs
Clock supply to UBC is halted
Description
DMAC runs
Clock supply to DMAC halted
Description
DAC runs
Clock supply to DAC halted
(Initial value)
(Initial value)
(Initial value)
(Initial value)