HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 610

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 18 Smart Card Interface
18.3.5
Only the internal clock generated by the on-chip baud rate generator can be used as the
communication clock in the smart card interface. The bit rate for the clock is set by the bit rate
register (SCBRR) and the CKS1 and CKS0 bits in the serial mode register (SCSMR), and is
calculated using the equation below. Table 18.5 shows sample bit rates. If clock output is then
selected by setting CKE0 to 1, a clock with a frequency 372 times the bit rate is output from the
SCK0 pin.
Where: N = Value set in SCBRR (0 ≤ N ≤ 255)
Rev.6.00 Mar. 27, 2009 Page 552 of 1036
REJ09B0254-0600
In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z, and
communication is MSB first. The start character data is H'3F. The parity bit is even (from the
smart card standards), and thus 0, which corresponds to state Z.
Only data bits D7 to D0 are inverted by the SINV bit. To invert the parity bit, set the O/E bit in
SCSMR to odd parity mode. This applies to both transmission and reception.
(Z)
(Z)
B =
B = Bit rate (bit/s)
Pφ = Peripheral module operating frequency (MHz)
n = 0 to 3 (table 18.4)
Clock
1488 × 2
Ds
Ds
A
A
Z
D0
Z
D7
2n−1
b. Inverse convention (SDIR, SINV, and O/E are all 1)
Pφ
a. Direct convention (SDIR, SINV, and O/E are all 0)
× (N + 1)
Figure 18.4 Waveform of Start Character
Z
D1
Z
D6
A
D2
A
D5
× 10
6
Z
D3
A
D4
Z
D4
A
D3
Z
D5
A
D2
A
D6
A
D1
A
D7
A
D0
Dp
Dp
Z
Z
(Z)
(Z)
State
State