HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 537

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 16 Realtime Clock (RTC)
16.4.3
Using the ADJ Bit in the Real Time Clock (RTC)
(1) Description
The maximum amount of time from when the ADJ bit in RCR2 of the RTC is set to 1 and when
the value read from the second counter (RSECCNT) is reflected is approximately 91.6 µs (the
time required for pin of the EXTAL2 to connect to the 32.768 kHz crystal resonator). Note that the
second counter itself performs a 30-second adjustment when the ADJ bit is set to 1, so the above
delay causes no problems with the functioning of the RTC.
(2) Precautions
If it is necessary to ensure that the 30-second adjustment triggered by the ADJ bit in RCR2 of the
RTC is properly read and its value reflected, the second counter should not be read until a
minimum of approximately 91.6 µs has passed following the setting of the ADJ bit.
Rev.6.00 Mar. 27, 2009 Page 479 of 1036
REJ09B0254-0600