HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 552

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
Section 17 Serial Communication Interface (SCI)
Bits 1 and 0—Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCI clock source
and enable or disable clock output from the SCK0 pin. Depending on the combination of CKE1
and CKE0, the SCK0 pin can be used for serial clock output or serial clock input.
The CKE0 setting is valid only when the asynchronous mode and the internal clock are selected
(CKE1 = 0). The CKE0 setting is ignored in the clock synchronous mode, or when an external
clock source is selected (CKE1 = 1). Before selecting the SCI operating mode in the serial mode
register (SCSMR), set CKE1 and CKE0. For further details on selection of the SCI clock source,
see table 17.10 in section 17.3, Operation.
Bit 1:
CKE1
0
1
Notes: 1. Initial value
Rev.6.00 Mar. 27, 2009 Page 494 of 1036
REJ09B0254-0600
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
Bit 0:
CKE0
0
1
0
1
Description
Asynchronous mode
Clock synchronous mode
Asynchronous mode
Clock synchronous mode
Asynchronous mode
Clock synchronous mode
Asynchronous mode
Clock synchronous mode
Internal clock, SCK0 pin used for input pin (input
signal is ignored) *
Internal clock, SCK0 pin used for synchronous clock
output *
Internal clock, SCK0 pin used for clock output *
Internal clock, SCK0 pin used for synchronous clock
output
External clock, SCK0 pin used for clock input *
External clock, SCK0 pin used for synchronous
clock input
External clock, SCK0 pin used for clock input *
External clock, SCK0 pin used for synchronous
clock input
1
1
3
3
2

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