HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 675

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit 9—Transmit Enable (TXE): Setting of this bit becomes effective when next frame starts (at
the rising edge of frame synchronize signal)and data are stored in transmit FIFO. After the setting
“1” to this bit becomes effective, SIOF submit the transmit request according to the TFWM bit of
SIFCTR register. When data is sets to transmit FIFO, transmit data is transfer from TXD_SIO.
This bit is initialized at transmit reset.
Bit 9: TXE
0
1
Bit 8—Receive Enable (RXE): Setting of this bit is effective when next frame starts (at the rising
edge of frame synchronizing signal). After the setting “1” to this bit becomes effective, SIOF
begins to receive the data from RXD_SIO. When data is sets to the receive FIFO, SIOF submits
the request to transfer according to RFWM bit of SIFCTR register. This bit is initialized at receive
reset.
Bit 8: RXE
0
1
Bit 1—Transmitting Operation Reset (TXRST): Setting to this bit becomes effective
immediately. After the setting 1 to this bit becomes effective, SIOF change transmit data from
TXD_SIO to 1 and initializes the following registers.
1. SITDR register
2. Transmit FIFO write pointer and read pointer
3. TCRDY, TFEMP, and TDREQ bits of SISTR register
4. TXE bit
SIOF is cleared automatically when this bit completes the reset, so 0 is always read from this bit.
Bit 1: TXRST
0
1
Description
Disable to transmit data from TXD_SIO (outputs 1)
Enable to transmit data from TXD_SIO
Description
Disable to receive data from RXD_SIO
Enable to receive data from RXD_SIO
Description
Transmitting operation is not reset
Transmitting operation is reset
Rev.6.00 Mar. 27, 2009 Page 617 of 1036
Section 20 Serial IO (SIOF)
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)