HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 635

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit 6—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, the SCFTDR2 did not contain valid data, so transmission has ended.
Bit 6: TEND
0
1
Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data is transferred from transmit
FIFO data register 2 (SCFTDR2) to transmit shift register (SCTSR), the quantity of data in
SCFTDR2 becomes less than the number of transmission triggers specified by the TTRG1 and
TTRG0 bits in FIFO control register 2 (SCFCR2), and writing the transmit data to SCFTDR2 is
enabled.
Bit 5: TDFE
0
1
Note: * Since SCFTDR2 is a 16-byte FIFO register, the maximum quantity of data which can be
written when TDFE is 1 is “16 minus the specified number of transmission triggers.” If an
attempt is made to write additional data, the data is ignored. The quantity of data in
SCFTDR2 is indicated by the upper 8 bits of SCFTDR2.
Description
Transmission is in progress.
TEND is cleared to 0 when data is written in SCFTDR2.
End of transmission.
TEND is set to 1 when the chip is reset or enters standby mode, TE is cleared to
0 in the serial control register (SCSCR2), or when SCFTDR2 does not contain
received data when the last bit of a one-byte serial character is transmitted.
Description
The quantity of transmit data written to SCFTDR2 is greater than the specified
number of transmission triggers.
TDFE is cleared to 0 when data exceeding the specified transmission trigger
number is written to SCFTDR2, and software reads 1 from TDFE and then writes
0 to TDFE.
The quantity of transmit data in SCFTDR2 is less than the specified number of
transmission triggers.*
TDFE is set to 1 at reset or at standby mode, or when the quantity of
transmission data in SCFTDR2 becomes less than the specified number of
transmission triggers as a result of transmission.
Section 19 Serial Communication Interface with FIFO (SCIF)
Rev.6.00 Mar. 27, 2009 Page 577 of 1036
REJ09B0254-0600
(Initial value)
(Initial value)