HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 834

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 25 LCD Controller
25.2.7
LDLAOR sets the address width of the Y-coordinates increment used for LCDC to read the image
recognized by the graphics driver. This register specifies how many bytes the address from which
data is to be read should be moved when the Y coordinates (vertical direction) have been
incremented by 1. This register does not have to be equal to the horizontal width of the LCD
panel. When the memory address of a point (X, Y) in the two-dimensional image is calculated by
Ax + By+ C, this register becomes equal to B in this equation.
Bits 15 to 0—Line Address Offset (LDLAOR)
Notes: 1. The minimum alignment unit of LDLAOR is four bytes. Because the LCDC handles
Rev.6.00 Mar. 27, 2009 Page 776 of 1036
REJ09B0254-0600
Initial value:
R/W:
Bit:
2. A binary exponential at least as large as the horizontal width of the image is
LAO15 LAO14 LAO13 LAO12 LAO11 LAO10 LAO9
LCDC Line Address Offset Register for Display Data Fetch (LDLAOR)
R/W
15
these values as longword data, the values written to the lower two bits of the register
are always treated as 0. The lower two bits of the register are always read as 0. The
initial values (
×
table 25.3, in section 25.3, Operation.
recommended for the LDLAOR value, taking into consideration the software operation
speed. When the hardware rotation function is used (ROT = 1), the LDLAOR value
should be a binary exponential (in this example, 256) at least as large as the horizontal
width of the image (after rotation, it becomes 240 in a 240
horizontal width of the LCD panel (320 in a 320
0
480 dots) display data without skipping an address between lines. For details, see
R/W
14
0
R/W
13
0
×
R/W
resolution = 640) will continuously and accurately place the VGA (640
12
0
R/W
11
0
R/W
10
0
R/W
9
1
LAO8
R/W
8
0
LAO7
R/W
7
1
×
LAO6
R/W
240 panel).
6
0
LAO5
R/W
5
0
×
LAO4
320 panel) instead of the
R/W
4
0
LAO3
R/W
3
0
LAO2
R/W
2
0
LAO1
R/W
1
0
LAO0
R/W
0
0