HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 500

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 14 Direct Memory Access Controller (DMAC)
14. Do not use the DMAC when in sleep mode. Alternately, set the clock ratio to Iφ:Bφ = 1:1
15. Do not use the DMAC when only the IFC[2:0] bits in the frequency control register (FRQCR)
Rev.6.00 Mar. 27, 2009 Page 442 of 1036
REJ09B0254-0600
Measures to avoid the problem:
when using sleep mode. Normal operation cannot be guaranteed otherwise.
are modified and the clock ratio is set to other than Iφ:Bφ = 1:1. Normal operation cannot be
guaranteed otherwise. However, there is no problem if the STC[2:0] bits are modified
simultaneously with the IFC[2:0] bits in the frequency control register (FRQCR).
The problem described above occurs only when all of the above conditions are met. It does
not arise if even one of the conditions is not met. One of the methods listed below should
therefore be employed when using the DMAC to transfer data from XY memory:
(1) Use the direct address mode
(2) Use long word size or word size data
(3) Use big-endian data transfer