HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 821

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

25.1
A unified memory architecture is adopted for the LCD controller (LCDC) so that the image data
for display is stored in system memory. The LCDC module reads data from system memory, uses
the pallet memory to determine the colors, then puts the display on the LCD panel. It is possible to
connect the LCDC to the LCD module of most types other than microcomputer bus interface types
and NTSC/PAL types and those that apply the LVDS interface∗.
Note: * An LVDS-conversion LSI can be connected to the LCDC to allow connection to an
25.1.1
The LCDC has the following features.
• Panel interface
• Supports 4/8/15/16-bpp (bit per pixel) color modes
• Supports 1/2/4/6-bpp grayscale modes
• Supports LCD-panel sizes from 16 × 1 to 1024 × 1024
• 24-bit color palette memory (16 of the 24 bits are valid; R:5/G:6/B:5)
• STN/DSTN panels are prone to flicker and shadowing. The controller applies 65536-color
• Dedicated display memory is unnecessary because the controller uses synchronous DRAM
• The display is stable because of the large 2.4-kbyte line buffer
• Supports the inversion of the output signal to suit the LCD panel’s signal polarity
• Supports variation of the burst length in reading from the synchronous DRAM, to realize high-
• Supports the selection of data formats (the endian setting for bytes, backed pixel method) by
• A hardware-rotation mode is included to support the use of landscape-format LCD panels as
⎯ Serial interface method
⎯ Supports data formats for STN/dual-STN/TFT panels (8/12/16/18-bit bus width)
control by 24-bit space-modulation FRC with 8-bit RGB values for reduced flicker.
which is connected to area 3 of the CPU’s memory map
speeds in the reading of data
register settings
portrait-format LCD panels (the horizontal width of the panel before rotation must be within
320 pixels—see table 25.3).
LVDS interface.
Overview
Features
Section 25 LCD Controller
Rev.6.00 Mar. 27, 2009 Page 763 of 1036
Section 25 LCD Controller
REJ09B0254-0600