NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 101

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Intel
Table 34.
Intel
®
®
SPI_CS[1:0]#
Signal Name
ICH8 Family Datasheet
CL_DATA 0
CL_DATA 1
ICH8 Pin States
SPI_MOSI
CL_CLK 0
CL_CLK 1
CL_RST#
SPI_CLK
Power Plane and States for Output and I/O Signals for Mobile Configurations
(Sheet 4 of 4)
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
ICH8 drives these signals High after the CPU Reset
GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH8 comes out of
reset
CPUPWRGD represents a logical AND of the ICH8’s VRMPWRGD and PWROK signals, and
thus will be driven low by ICH8 when either VRMPWRGD or PWROK are inactive. During
boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition
from low to High-Z.
The states of Core and processor signals are evaluated at the times During PLTRST# and
Immediately after PLTRST#. The states of the LAN and GLAN signals are evaluated at the
times During LAN_RST# and Immediately after LAN_RST#. The states of the Controller
Link signals are evaluated at the times During CL_RST# and Immediately after CL_RST#.
The states of the Suspend signals are evaluated at the times During RSMRST# and
Immediately after RSMRST#. The states of the HDA signals are evaluated at the times
During HDA_RST# and Immediately after HDA_RST#.
ICH8 drives these signals Low before PWROK rising and Low after the processor Reset.
SLP_S5# signals will be high in the S4 state.
Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset
HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be
Running.
PETp/n[6:1] high until port is enabled by software.
The SLP_M# state will be determined by AMT policies
Controller
Controller
Controller
Controller
Suspend
Suspend
Power
Plane
Link
Link
Link
Link
During
Reset
High
High
Low
Low
Low
Low
4
Controller Link
SPI Interface
Immediately
after Reset
High
High
High
Low
Low
Low
4
C3/C4
High
High
High
Low
Low
Low
High
High
High
Low
Low
Low
S1
High
Off
Off
Off
Off
Off
S3
S4/S5
High
Off
Off
Off
Off
Off
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