NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 216

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.19.7
5.19.7.1
5.19.7.2
5.19.7.3
216
USB 2.0 Power Management
USB Pre-Fetch Pause Feature
The Pre-Fetch Based Pause is a power management feature in USB (EHCI) host
controllers to ensure maximum C3/C4 CPU power state time with C2 popup. This
feature applies to the period schedule and works by allowing the DMA engine to identify
periods of idleness and prevents the DMA engine from accessing memory when the
periodic schedule is idle. Typically in the presence of periodic devices with multiple
millisecond poll periods, the periodic schedule will be idle for several frames between
polls.
The USB Pre-Fetch Based Pause feature is disabled by setting bit 4 of EHCI
Configuration Register
Suspend Feature
The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification,
Section 4.3 describes the details of Port Suspend and Resume.
ACPI Device States
The USB 2.0 function only supports the D0 and D3 PCI Power Management states.
Notes regarding the ICH8 implementation of the Device States:
1. The EHC hardware does not inherently consume any more power when it is in the
2. In the D0 state, all implemented EHC features are enabled.
3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort.
4. In the D3 state, the EHC interrupt must never assert for any reason. The internal
5. When the Device Power State field is written to D0 from D3, an internal reset is
6. Attempts to write any other value into the Device Power State field other than 00b
D0 state than it does in the D3 state. However, software is required to suspend or
disable all ports prior to entering the D3 state such that the maximum power
consumption is reduced.
Note that, since the Debug Port uses the same memory range, the Debug Port is
only operational when the EHC is in the D0 state.
PME# signal is used to signal wake events, etc.
generated. See section EHC Resets for general rules on the effects of this reset.
(D0 state) and 11b (D3 state) will complete normally without changing the current
value in this field.
Section
15.1.30.
Intel
®
Functional Description
ICH8 Family Datasheet