NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 603

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EHCI Controller Registers (D29:F7, D26:F7)
15.2
Note:
Note:
15.2.1
Note:
Note:
Table 134.
Intel
®
ICH8 Family Datasheet
Enhanced Host Controller Capability Registers
Memory-Mapped I/O Registers
The EHCI memory-mapped I/O space is composed of two sets of registers: Capability
Registers and Operational Registers.
The ICH8 EHCI controller will not accept memory transactions (neither reads nor
writes) as a target that are locked transactions. The locked transactions should not be
forwarded to PCI as the address space is known to be allocated to USB.
When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory
range are ignored and result a master abort. Similarly, if the Memory Space Enable
(MSE) bit (D29:F7, D26:F7:04h, bit 1) is not set in the Command register in
configuration space, the memory range will not be decoded by the ICH8 enhanced host
controller (EHC). If the MSE bit is not set, then the ICH8 must default to allowing any
memory accesses for the range specified in the BAR to go to PCI. This is because the
range may not be valid and, therefore, the cycle must be made available to any other
targets that may be currently using that range.
Host Controller Capability Registers
These registers specify the limits, restrictions and capabilities of the host controller
implementation. Within the host controller capability registers, only the structural
parameters register is writable. These registers are implemented in the suspend well
and is only reset by the standard suspend-well hardware reset, not by HCRESET or the
D3-to-D0 reset.
Note that the EHCI controller does not support as a target memory transactions that
are locked transactions. Attempting to access the EHCI controller Memory-Mapped I/O
space using locked memory transactions will result in undefined behavior.
Note that when the USB2 function is in the D3 PCI power state, accesses to the USB2
memory range are ignored and will result in a master abort Similarly, if the Memory
Space Enable (MSE) bit is not set in the Command register in configuration space, the
memory range will not be decoded by the Enhanced Host Controller (EHC). If the MSE
bit is not set, then the EHC will not claim any memory accesses for the range specified
in the BAR.
NOTE: “Read/Write Special” means that the register is normally read-only, but may be written
MEM_BASE
+ Offset
08h–0Bh
02h–03h
04h–07h
00h
when the WRT_RDONLY bit is set. Because these registers are expected to be programmed
by BIOS during initialization, their contents must not get modified by HCRESET or D3-to-
D0 internal reset.
HCIVERSION
HCSPARAMS
HCCPARAMS
CAPLENGTH
Mnemonic
Capabilities Registers Length
Host Controller Interface Version
Number
Host Controller Structural Parameters
Host Controller Capability Parameters
Register
00104208h
00006871h
Default
0100h
20h
(special),
Type
R/W
RO
RO
RO
RO
603