NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 73

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Description
Table 16.
Intel
®
ICH8 Family Datasheet
Power Management Interface Signals (Sheet 2 of 4)
S4_STATE#/
PWRBTN#
CLPWROK
SLP_S4#
SLP_S5#
SLP_M#
PWROK
GPIO26
Name
RI#
Type
O
O
O
O
I
I
I
I
S4 Sleep Control: SLP_S4# is for power plane control. This signal
shuts power to all non-critical systems when in the S4 (Suspend to
Disk) or S5 (Soft Off) state.
NOTE: This pin must be used to control the DRAM power in order to
NOTE: In a system with Intel AMT support, this signal should be used
S5 Sleep Control: SLP_S5# is for power plane control. This signal is
used to shut power off to all non-critical systems when in the S5 (Soft
Off) states.
Manageability Sleep State Control: This signal is used to control
power planes to the Intel AMT sub-system. IF no ME firmware is
present, SLP_M# will have the same timings as SLP_S3#.
S4 State Indication: This signals asserts low when the host platform
is in S4 or S5 state. In platforms where the manageability engine is
forcing the SLP_S4# high along with SLP_M#, this signal can be used
by other devices on the board to know when the host platform is below
the S3 state.
Power OK: When asserted, PWROK is an indication to the ICH8 that
all power rails have been stable for 99 ms and that PCICLK has been
stable for 1 ms. PWROK can be driven asynchronously. When PWROK is
negated, the ICH8 asserts PLTRST#.
NOTE: PWROK must deassert for a minimum of three RTC clock
Controller Link Power OK: When asserted, this signal indicates that
power to the Controller Link subsystem ((G)MCH, ICH8, etc.) is stable
and tells the ICH8 to deassert CL_RST# to the (G)MCH.
NOTES:
1.
2.
Power Button: The Power Button will cause SMI# or SCI to indicate a
system request to go to a sleep state. If the system is already in a
sleep state, this signal will cause a wake event. If PWRBTN# is pressed
for more than 4 seconds, this will cause an unconditional transition
(power button override) to the S5 state. Override will occur even if the
system is in the S1-S4 states. This signal has an internal pull-up
resistor and has an internal 16 ms de-bounce on the input.
Ring Indicate: This signal is an input from a modem. It can be
enabled as a wake event, and this is preserved across power failures.
use the ICH8’s DRAM power-cycling feature. Refer to
Chapter 5.13.11.2
to control the DRAM power. In M1 state (where the host
platform is in S3-S5 states and the manageability sub-system
is running) the signal is forced high along with SLP_M# in order
to properly maintain power to the DIMM used for manageability
sub-system.
periods in order for the ICH8 to fully reset the power and
properly generate the PLTRST# output.
CLPWROK must not assert before RSMRST# deasserts
CLPWROK must not assert after PWROK asserts
for details
Description
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