NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 51

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Introduction
Intel
®
ICH8 Family Datasheet
IDE Interface (Bus Master Capability and Synchronous DMA Mode) (Mobile
Only)
The fast IDE interface supports up to two IDE devices providing an interface for IDE
hard disks and ATAPI devices. Each IDE device can have independent timings. The IDE
interface supports PIO IDE transfers up to 16 MB/sec and Ultra ATA transfers up
100 MB/sec. It does not consume any legacy DMA resources. The IDE interface
integrates 16x32-bit buffers for optimal transfers.
The ICH8’s IDE system contains a single, independent IDE signal channel that can be
electrically isolated. There are integrated series resistors on the data and control lines
(see
availability.
Low Pin Count (LPC) Interface
The ICH8 implements an LPC Interface as described in the LPC 1.1 Specification. The
Low Pin Count (LPC) bridge function of the ICH8 resides in PCI Device 31:Function 0. In
addition to the LPC bridge interface function, D31:F0 contains other functional units
including DMA, interrupt controllers, timers, power management, system management,
GPIO, and RTC.
Serial Peripheral Interface (SPI)
The ICH8 implements an SPI Interface as an alternative interface for the BIOS flash
device. An SPI flash device can be used as a replacement for the FWH, and is required
to support Intel Active Management Technology (ICH8DO and ICH8M-E only) and the
integrated Fan Speed Control (Intel
ICH8 supports up to two SPI flash devices with speeds up to 33 MHz using two chip
select pins.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-
byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any
two of the seven DMA channels can be programmed to support fast Type-F transfers.
The ICH8 supports LPC DMA, which is similar to ISA DMA, through the ICH8’s DMA
controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals
and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and
Increment modes are supported on the LPC interface. Channels 0–3 are 8-bit channels.
Channels 5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master
request.
The timer/counter block contains three counters that are equivalent in function to those
found in one 82C54 programmable interval timer. These three counters are combined
to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator
input provides the clock source for these three counters.
The ICH8 provides an ISA-Compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt
controllers are cascaded so that 14 external and two internal interrupts are possible. In
addition, the ICH8 supports a serial interrupt scheme.
All of the registers in these modules can be read and restored. This is required to save
and restore system state after power has been removed and restored to the platform.
Section 5.17
for details). See
Section 1.2
®
Quiet System Technology) (Desktop only). The
for details on component feature
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