NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 779

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (SPI)
20.3.3
Intel
®
ICH8 Family Datasheet
HSFC—Hardware Sequencing Flash Control Register
(
Memory Address:GLBAR + 06h
Default Value:
15:10
GbE LAN Memory Mapped Configuration Registers
9:8
Bit
Bit
1
0
Flash Cycle Error (FCERR) — R/W/C. Hardware sets this bit to 1 when an program
register access is blocked to the FLASH due to one of the protection policies or when
any of the programmed cycle registers is written while a programmed access is already
in progress. This bit remains asserted until cleared by software writing a 1 or until
hardware reset occurs. Software must clear this bit before setting the FLASH Cycle GO
bit in this register.
Hardware reset is initiated by one of the following resets:
Flash Cycle Done (FDONE) — R/W/C. The ICH8 sets this bit to 1 when the SPI Cycle
completes after software previously set the FGO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset. When this bit is set and the SPI
SMI# Enable bit is set, an internal signal is asserted to the SMI# generation block.
Software must make sure this bit is cleared prior to enabling the SPI SMI# assertion for
a new programmed access.
Hardware reset is initiated by one of the following resets:
Reserved
Flash Data Byte Count (FDBC): — R/W. This field specifies the number of bytes to
shift in or out during the data portion of the SPI cycle. The content’s of this register are
0’s based with 0b representing 1 byte and 11b representing 4 bytes. The number of
bytes transferred is the value of this field plus 1.
This field is ignored for the Block Erase command.
• Global reset (when the Host and the ME partitions are both reset) - on both ME-enabled and
• Host Partition reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on
• Global reset (when the Host and the ME partitions are both reset) - on both ME-enabled and
• Host Partition reset (any time PLTRST# is asserted either from a cold or a warm reset) - only on
non-ME systems.
ME enabled systems.
non-ME systems.
ME enabled systems.
0000h
Description
Description
Attribute:
Size:
R/W, R/WS
16 bits
)
779