NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 176

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.13.9.5
Note:
5.13.9.6
176
THRMTRIP# Signal
If THRMTRIP# goes active, the processor is indicating an overheat condition, and the
ICH8 immediately transitions to an S5 state. However, since the processor has
overheated, it does not respond to the ICH8’s STPCLK# pin with a stop grant special
cycle. Therefore, the ICH8 does not wait for one. Immediately upon seeing THRMTRIP#
low, the ICH8 initiates a transition to the S5 state, drive SLP_S3#, SLP_S4#, SLP_S5#
low, and set the CTS bit. The transition looks like a power button override.
It is extremely important that when a THRMTRIP# event occurs, the ICH8 power down
immediately without following the normal S0 -> S5 path. This path may be taken in
parallel, but ICH8 must immediately enter a power down state. It does this by driving
SLP_S3#, SLP_S4#, and SLP_S5# immediately after sampling THRMTRIP# active.
If the processor is running extremely hot and is heating up, it is possible (although very
unlikely) that components around it, such as the ICH8, are no longer executing cycles
properly. Therefore, if THRMTRIP# goes active, and the ICH8 is relying on state
machine logic to perform the power down, the state machine may not be working, and
the system will not power down.
The ICH8 follows this flow for THRMTRIP#.
During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, VRMPWRGD/VGATE, and
PLTRST# are all ‘1’. During entry into a powered-down state (due to S3, S4, S5 entry,
power cycle reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or PWROK =
0, or VRMPWRGD/VGATE = 0.
A thermal trip event will:
BMBUSY# (Mobile Only)
The BMBUSY# signal is an input from a graphics component to indicate if it is busy. If
prior to going to the C3 state, the BMBUSY# signal is active, then the BM_STS bit will
be set. If after going to the C3 state, the BMBUSY# signal goes back active, the ICH8
will treat this as if one of the PCI REQ# signals went active. This is treated as a break
event.
1. At boot (PLTRST# low), THRMTRIP# ignored.
2. After power-up (PLTRST# high), if THRMTRIP# sampled active, SLP_S3#,
3. Until sleep machine enters the S5 state, SLP_S3#, SLP_S4#, and SLP_S5# stay
4. If S5 state reached, go to step #1, otherwise stay here. If the ICH8 never reaches
• Set the AFTERG3_EN bit
• Clear the PWRBTN_STS bit
• Clear all the GPE0_EN register bits
• Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave
SLP_S4#, and SLP_S5# assert, and normal sequence of sleep machine starts.
active, even if THRMTRIP# is now inactive. This is the equivalent of “latching” the
thermal trip event.
S5, the ICH8 does not reboot until power is cycled.
receiving message and not set due to SMBAlert
Intel
®
Functional Description
ICH8 Family Datasheet