NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 460

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.1.25
460
IDE_CONFIG—IDE I/O Configuration Register
(IDE—D31:F1)
Address Offset:
Default Value:
31:24
23:20
19:18
17:16
15:14
11:8
3:2
Bit
13
12
7
6
5
4
1
0
Reserved
Miscellaneous Scratchpad (MS) — R/W. Previously defined as a scratchpad bit to
indicate to a driver that ATA-100 is supported. This is not used by software as all they
needed to know was located in bits 7:4. See the definition of those bits.
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the ICH8M.
SIG_MODE — R/W. These bits are used to control mode of the IDE signal pins for swap
bay support.
If the PRS bit (Chipset Config Registers:Offset 3414h:bit 1) is 1, the reset states of bits
17:16 will be 01 (tri-state) instead of 00 (normal).
00 = Normal (Enabled)
01 = Tri-state (Disabled)
10 = Drive low (Disabled)
11 = Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the ICH8M.
Fast Primary Drive 1 Base Clock (FAST_PCB1) — R/W. This bit is used in
conjunction with the PCT1 bits to enable/disable Ultra ATA/100 timings for the Primary
Slave drive.
0 = Disable Ultra ATA/100 timing for the Primary Slave drive.
1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this register).
Fast Primary Drive 0 Base Clock (FAST_PCB0) — R/W. This bit is used in
conjunction with the PCT0 bits to enable/disable Ultra ATA/100 timings for the Primary
Master drive.
0 = Disable Ultra ATA/100 timing for the Primary Master drive.
1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this register).
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the ICH8M.
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the ICH8M.
Primary Slave Channel Cable Reporting — R/W. BIOS should program this bit to tell
the IDE driver which cable is plugged into the channel.
0 = 40 conductor cable is present.
1 = 80 conductor cable is present.
Primary Master Channel Cable Reporting — R/W. Same description as bit 5
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility,
but have no functionality in the ICH8M.
Primary Drive 1 Base Clock (PCB1) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Primary Drive 0 Base Clock (PCB0) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
54h
00000000h
Description
Attribute:
Size:
IDE Controller Registers (D31:F1) (Mobile Only)
R/W
32 bits
Intel
®
ICH8 Family Datasheet