NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 626

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.1.2
16.1.3
626
DID—Device Identification Register (SMBUS—D31:F3)
Address:
Default Value:
PCICMD—PCI Command Register (SMBUS—D31:F3)
Address:
Default Value:
15:11
15:0
Bit
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W.
0 = Enable
1 = Disables SMBus to assert its PIRQB# signal.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W.
0 = Enables SERR# generation.
1 = Disables SERR# generation.
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — R/W.
0 = Disable
1 = Sets Detected Parity Error bit (D31:F3:06, bit 15) when a parity error is detected.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — RO. Hardwired to 0.
Memory Space Enable (MSE) — R/W.
0 = Disables memory mapped configuration space.
1 = Enables memory mapped configuration space.
I/O Space Enable (IOSE) — R/W.
0 = Disable
1 = Enables access to the SM Bus I/O space registers as defined by the Base Address
Device ID — RO. This is a 16-bit value assigned to the Intel® ICH8 SMBus controller.
Refer to the Intel
Register.
Register.
02h
See bit description
04h
0000h
–
–
03h
05h
®
ICH8 Family Specification Update for the value of the Device ID
Description
Description
Attribute:
Size:
Attributes:
Size:
SMBus Controller Registers (D31:F3)
RO
16 bits
RO, R/W
16 bits
Intel
®
ICH8 Family Datasheet