NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 851

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
23.5
Figure 22.
Figure 23.
Intel
®
ICH8 Family Datasheet
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Timing Diagrams
Clock Timing
Valid Delay from Rising Clock Edge
For t234 and t298, if Intel Manageability Engine firmware is installed in the system, the
Max value of t234 and t298 is 99 ms. Without the installation of the firmware, the Max
value is 4 RTC clocks.
RSMRST# must deassert before or equal to LAN_RST#
Measured from VccLAN3_3 or VccLAN1_05 pwr within voltage spec (which ever is later in
time) to LAN_RST# = (Vih+Vil)/2. It is acceptable to use an RC circuit sourced from
VccLAN3_3 to create LAN_RST#. The rising edge of LAN_RST# needs to be a clean,
monotonic edge for frequency content below 10MHz.
If Integrated LAN is supported, LAN_RST# must be deasserted before or equal to PWROK
assertion.
If Integrated LAN is not supported, LAN_RST# should be tied to ground and must never
deassert
RSMRST# falling edge must transition to 0.8V or less before VccSus3_3 drops to 2.1V
If bit 0 of
is detected. If bit 0 is set to 0, SLP_S5# will deassert within the specification listed in the
table.
t294 applies during S0 to G3 transitions only. The timing is not applied to V5REF. V5REF
timings are bonded by power sequencing.
t307 applies during S0 to Sx transitions.
A Vcc supply is inactive when the voltage is below the min value specified in
t313 is not applicable for non-Intel AMT systems. t313 applies to Mobile Intel AMT systems
only in case of S0/M0 to S4/S4Moff (w/o WOL).
t290 is also applied when the system transistions from S0 to G3.
Output
Clock
Section 9.8.1.3
0.8V
High Time
2.0V
Fall Time
is set to a 1, SLP_S5# will not be de-asserted until a wake event
1.5V
Valid Delay
Period
VT
Low Time
Rise Time
Table
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