NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 114

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
114
Power Management
S3/S4/S5 Support
Software initiates the transition to S3/S4/S5 by performing an IO write to the Power
Management Control register in the ICH8. After the IO write completion has been
returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction
Layer Packet) message on its downstream link. The device attached to the link will
eventually respond with a PME_TO_Ack TLP message followed by sending a
PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state.
When all of the ICH8 root ports links are in the L2/L3 Ready state, the ICH8 power
management control logic will proceed with the entry into S3/S4/S5.
Prior to entering S3, software is required to put each device into D3
is put into D3
DLLP. Thus under normal operating conditions when the root ports sends the
PME_Turn_Off message the link will be in state L1. However, when the root port is
instructed to send the PME_Turn_Off message, it will send it whether or not the link
was in L1. Endpoints attached to the ICH8 can make no assumptions about the state of
the link prior to receiving a PME_Turn_Off message.
Resuming from Suspended State
The root port contains enough circuitry in the resume well to detect a wake event
through the WAKE# signal and to wake the system. When WAKE# is detected asserted,
an internal signal is sent to the power management controller of the ICH8 to cause the
system to wake up. This internal message is not logged in any register, nor is an
interrupt/GPE generated due to it.
Device Initiated PM_PME Message
When the system has returned to a working state from a previous low power state, a
device requesting service will send a PM_PME message continuously, until acknowledge
by the root port. The root port will take different actions depending upon whether this
is the first PM_PME has been received, or whether a previous message has been
received but not yet serviced by the operating system.
If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit
16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID into
RSTS.RID (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bits 15:0). If an interrupt is enabled via
RCTL.PIE (D28:F0/F1/F2/F3/F4/F5:Offset 5Ch:bit 3), an interrupt will be generated.
This interrupt can be either a pin or an MSI if MSI is enabled via MC.MSIE (D28:F0/F1/
F2/F3/F4/F5:Offset 82h:bit 0). See
If this is a subsequent message received (RSTS.PS is already set), the root port will set
RSTS.PP (D28:F0/F1/F2/F3/F4/F5:Offset 60h:bit 17) and log the PME Requester ID
from the message in a hidden register. No other action will be taken.
When the first PME event is cleared by software clearing RSTS.PS, the root port will set
RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into
RSTS.RID.
If RCTL.PIE is set, generate an interrupt. If RCTL.PIE is not set, send over to the power
management controller so that a GPE can be set. If messages have been logged
(RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and interrupt must be
generated. This last condition handles the case where the message was received prior
to the operating system re-enabling interrupts after resuming from a low power state.
HOT
it will initiate entry into a L1 link state by sending a PM_Enter_L1
Section 5.2.2.4
for SMI/SCI generation.
Intel
HOT
®
Functional Description
ICH8 Family Datasheet
. When a device