NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 420

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.9.6
420
TCO1_CNT—TCO1 Control Register
I/O Address:
WC
Default Value:
Lockable:
15:13
Bit
Bit
12
11
10
9
0
Reserved
TCO_LOCK — R/W (special). When set to 1, this bit prevents writes from changing the
TCO_EN bit (in offset 30h of Power Management I/O space). Once this bit is set to 1, it
can not be cleared by software writing a 0 to this bit location. A core-well reset is
required to change this bit from 1 to 0. This bit defaults to 0.
TCO Timer Halt (TCO_TMR_HLT) — R/W.
0 = The TCO Timer is enabled to count.
1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will
Reserved
NMI2SMI_EN — R/W.
0 = Normal NMI functionality.
1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent
Intruder Detect (INTRD_DET) — R/WC.
0 = Software clears this bit by writing a 1 to it, or by RTCRST# assertion.
1 = Set by ICH8 to indicate that an intrusion was detected. This bit is set even if the
NOTE: This bit has a recovery time. After writing a 1 to this bit position (to clear it), the
NOTE: If the INTRUDER# signal is active when the software attempts to clear the
NOTE: If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is
NMI_EN
cause an SMI# or set the SECOND_TO_STS bit. When set, this bit will prevent
rebooting and prevent Alert On LAN event messages from being transmitted on the
SMLINK (but not Alert On LAN* heartbeat messages).
upon the settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the
following table:
system is in G3 state.
0b
0b
1b
1b
bit may be read back as a 1 for up 65 microseconds before it is read as a 0.
Software must be aware of this recovery time when reading this bit after
clearing it.
INTRD_DET bit, the bit will remain as a 1, and the SMI# will be generated again
immediately. The SMI handler can clear the INTRD_SEL bits (TCOBASE + 0Ah,
bits 2:1), to avoid further SMIs. However, if the INTRUDER# signals goes
inactive and then active again, there will not be further SMI’s (because the
INTRD_SEL bits would select that no SMI# be generated).
written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input
signal goes inactive. Note that this is slightly different than a classic sticky bit,
since most sticky bits would remain active indefinitely when the signal goes
active and would immediately go inactive when a 1 is written to the bit
TCOBASE +08h
0000h
No
GBL_SMI_EN
0b
1b
0b
1b
Description
No SMI# at all because GBL_SMI_EN = 0
SMI# will be caused due to NMI events
No SMI# at all because GBL_SMI_EN = 0
No SMI# due to NMI because NMI_EN = 1
Description
Description
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W, R/W (special), R/
16-bit
Core
Intel
®
ICH8 Family Datasheet