NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 541

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F5)
13.1.2
13.1.3
Intel
®
ICH8 Family Datasheet
DID—Device Identification Register (SATA—D31:F5)
Offset Address: 02h
Default Value:
Lockable:
PCICMD—PCI Command Register (SATA–D31:F5)
Address Offset: 04h
Default Value:
15:11
15:0
Bit
10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no
effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt and MSI is not
1 = Internal INTx# messages will not be generated.
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — R/W.
0 = Disabled. SATA controller will not generate PERR# when a data parity error is
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — R/W. This bit controls the ICH8’s ability to act as a PCI
master for IDE Bus Master transfers. This bit does not impact the generation of
completions for split transaction commands.
Memory Space Enable (MSE) — RO. This controller does not support AHCI, therefore
no memory space is required.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as
1 = Enable. Note that the Base Address register for the Bus Master registers should be
Device ID — RO. This is a 16-bit value assigned to the Intel
NOTE: The value of this field will change dependent upon the value of the MAP
enabled.
detected.
well as the Bus Master I/O registers.
programmed before this bit is set.
Register. See the Intel ICH8 Family Specification Update.
See bit description
No
0000h
–
–
03h
05h
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
®
RO
16 bit
Core
RO, R/W
16 bits
ICH8 SATA controller.
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