NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 37

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ICH8 Family Datasheet
Transfer Size Bit Definition ...................................................................................... 126
SYNC Bit Definition................................................................................................. 127
DMA Transfer Size.................................................................................................. 131
Address Shifting in 16-Bit I/O DMA Transfers ............................................................. 131
Counter Operating Modes........................................................................................ 137
Interrupt Controller Core Connections ....................................................................... 139
Interrupt Status Registers ....................................................................................... 140
Content of Interrupt Vector Byte .............................................................................. 140
APIC Interrupt Mapping .......................................................................................... 146
Interrupt Message Address Format ........................................................................... 148
Interrupt Message Data Format................................................................................ 149
Stop Frame Explanation .......................................................................................... 150
Data Frame Format ................................................................................................ 151
Configuration Bits Reset by RTCRST# Assertion ......................................................... 154
INIT# Going Active ................................................................................................ 156
NMI Sources.......................................................................................................... 157
DP Signal Differences ............................................................................................. 158
General Power States for Systems Using Intel
State Transition Rules for Intel
System Power Plane ............................................................................................... 162
Causes of SMI# and SCI ......................................................................................... 163
Break Events (Mobile Only) ..................................................................................... 166
Sleep Types .......................................................................................................... 170
Causes of Wake Events ........................................................................................... 170
GPI Wake Events ................................................................................................... 171
Transitions Due to Power Failure .............................................................................. 172
Transitions Due to Power Button .............................................................................. 174
Transitions Due to RI# Signal .................................................................................. 175
Write Only Registers with Read Paths in ALT Access Mode ........................................... 178
PIC Reserved Bits Return Values .............................................................................. 180
Register Write Accesses in ALT Access Mode .............................................................. 180
Intel
TCO Legacy/Compatible Mode SMBus Configuration .................................................... 186
Event Transitions that Cause Messages ..................................................................... 186
Interrupt/Active Bit Interaction Definition .................................................................. 193
SATA Feature Support ............................................................................................ 196
SATA Feature Support ............................................................................................ 197
Legacy Replacement Routing ................................................................................... 203
Bits Maintained in Low Power States ......................................................................... 210
USB Legacy Keyboard State Transitions .................................................................... 211
UHCI vs. EHCI ....................................................................................................... 213
Debug Port Behavior .............................................................................................. 221
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Enable for SMBALERT# ........................................................................................... 231
Enables for SMBus Slave Write and SMBus Host Events ............................................... 231
Enables for the Host Notify Command ....................................................................... 231
Slave Write Registers ............................................................................................. 233
Command Types .................................................................................................... 234
Slave Read Cycle Format ........................................................................................ 235
Data Values for Slave Read Registers........................................................................ 235
Host Notify Format ................................................................................................. 237
Required Commands and Opcodes............................................................................ 247
Recommended Command and Opcode Associations .................................................... 248
PCI Devices and Functions....................................................................................... 256
IDE Transaction Timings (PCI Clocks) ...................................................................... 190
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C Block Read ...................................................................................................... 228
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ICH8 Clock Inputs ........................................................................................ 182
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ICH8 ...................................................................... 161
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ICH8.................................................. 160
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