NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 527

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F2)
12.4.2.6
Intel
®
ICH8 Family Datasheet
PxIE—Port [5:0] Interrupt Enable Register (D31:F2)
Address Offset: Port 0: ABAR + 114h
Default Value:
This register enables and disables the reporting of the corresponding interrupt to
system software. When a bit is set (‘1’) and the corresponding interrupt condition is
active, then an interrupt is generated. Interrupt sources that are disabled (‘0’) are still
reflected in the status registers.
Bit
Bit
31
30
29
28
27
26
25
24
4
3
2
1
0
Unknown FIS Interrupt (UFS) — RO. When set to ‘1’ indicates that an unknown FIS
was received and has been copied into system memory. This bit is cleared to ‘0’ by
software clearing the PxSERR.DIAG.F bit to ‘0’. Note that this bit does not directly
reflect the PxSERR.DIAG.F bit. PxSERR.DIAG.F is set immediately when an unknown
FIS is detected, whereas this bit is set when the FIS is posted to memory. Software
should wait to act on an unknown FIS until this bit is set to ‘1’ or the two bits may
become out of sync.
Set Device Bits Interrupt (SDBS) — R/WC. A Set Device Bits FIS has been received
with the I bit set and has been copied into system memory.
DMA Setup FIS Interrupt (DSS) — R/WC. A DMA Setup FIS has been received with
the I bit set and has been copied into system memory.
PIO Setup FIS Interrupt (PSS) — R/WC. A PIO Setup FIS has been received with the
I bit set, it has been copied into system memory, and the data related to that FIS has
been transferred.
Device to Host Register FIS Interrupt (DHRS) — R/WC. A D2H Register FIS has
been received with the I bit set, and has been copied into system memory.
Cold Presence Detect Enable (CPDE) — RO. Cold Presence Detect is not supported.
Task File Error Enable (TFEE) — R/W. When set, and GHC.IE and PxTFD.STS.ERR
(due to a reception of the error register from a received FIS) are set, the Intel
will generate an interrupt.
Host Bus Fatal Error Enable (HBFE) — R/W. When set, and GHC.IE and PxS.HBFS
are set, the ICH8 will generate an interrupt.
Host Bus Data Error Enable (HBDE) — R/W. When set, and GHC.IE and PxS.HBDS
are set, the ICH8 will generate an interrupt.
Host Bus Data Error Enable (HBDE) — R/W. When set, GHC.IE is set, and
PxIS.HBDS is set, the ICH8 will generate an interrupt.
Interface Non-fatal Error Enable (INFE) — R/W. When set, GHC.IE is set, and
PxIS.INFS is set, the ICH8 will generate an interrupt.
Reserved - Should be written as 0
Overflow Error Enable (OFE) — R/W. When set, and GHC.IE and PxS.OFS are set,
the ICH8 will generate an interrupt.
Port 1: ABAR + 194h
Port 2: ABAR + 214h
Port 3: ABAR + 294h (Desktop Only)
Port 4: ABAR + 314h (Desktop Only)
Port 5: ABAR + 394h (Desktop Only)
00000000h
Description
Description
Attribute:
Size:
R/W, RO
32 bits
®
ICH8
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