NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 181

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.13.11.2
Note:
5.13.11.3
Note:
5.13.11.4
5.13.11.5
Intel
®
ICH8 Family Datasheet
SLP_S4# and Suspend-To-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic. The
SLP_S4# signal should be used to remove power to system memory rather than the
SLP_S5# signal. The SLP_S4# logic in the ICH8 provides a mechanism to fully cycle
the power to the DRAM and/or detect if the power is not cycled for a minimum time.
To utilize the minimum DRAM power-down feature that is enabled by the SLP_S4#
Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled
by the SLP_S4# signal.
PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid.
PWROK should go active no sooner than 100 ms after Vcc3_3 and Vcc1_5 have reached
their nominal values.
CPUPWRGD Signal
This signal is connected to the processor’s VRM via the VRMPWRGD signal and is
internally AND’d with the PWROK signal that comes from the system power supply.
VRMPWRGD Signal
VRMPWRGD is an input from the regulator indicating that all of the outputs from the
regulator are on and within specification. VRMPWRGD may go active before or after the
PWROK from the main power supply. ICH8 has no dependency on the order in which
these two signals go active or inactive. However, platforms that use the VRMPWRGD
signal to start the clock chip PLLs assume that it does assert milliseconds before
PWROK in order to provide valid clocks in time for the PWROK rising.
1. SYSRESET# is recommended for implementing the system reset button. This saves
2. If the PWROK input is used to implement the system reset button, the ICH8 does
3. If a design has an active-low reset button electrically AND’d with the PWROK signal
4. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that
5. In the case of true PWROK failure, PWROK goes low first before the VRMPWRGD.
6. When PWROK goes inactive, a host power cycle and global reset will occur. A host
external logic that is needed if the PWROK input is used. Additionally, it allows for
better handling of the SMBus and processor resets, and avoids improperly
reporting power failures.
not provide any mechanism to limit the amount of time that the processor is held in
reset. The platform must externally assure that maximum reset assertion specs are
met.
from the power supply and the processor’s voltage regulator module the ICH8
PWROK_FLR bit will be set. The ICH8 treats this internally as if the RSMRST# signal
had gone active. However, it is not treated as a full power failure. If PWROK goes
inactive and then active (but RSMRST# stays high), then the ICH8 reboots
(regardless of the state of the AFTERG3 bit). If the RSMRST# signal also goes low
before PWROK goes high, then this is a full power failure, and the reboot policy is
controlled by the AFTERG3 bit.
are less than one RTC clock period may not be detected by the ICH8.
power cycle is the assertion of SLP_S3#, SLP_S4#, and SLP_S5#, and the
deassertion of these signals 3-5 seconds later. The ME remains powered throughout
this cycle.
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