NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 500

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

500
(Desktop
(Mobile
Only)
Only)
Bits
7:2
1:0
10
9
9
8
BIST FIS Failed (BFF) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a BIST FIS transmitted by ICH8 receives an R_ERR
NOTE: This bit must be cleared by software prior to initiating a BIST FIS.
Port 1 BIST FIS Initiate (P1BFI) — R/W. When a rising edge is detected on this bit
field, the ICH8 initiates a BIST FIS to the device on Port 1, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 1 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
FISes or to return the ICH8 to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P1BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully
Reserved.
Port 0 BIST FIS Initiate (P0BFI) — R/W. When a rising edge is detected on this bit
field, the ICH8 initiates a BIST FIS to the device on Port 0, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 0 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
FISes or to return the ICH8 to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P0BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully
BIST FIS Parameters. These 6 bits form the contents of the upper 6 bits of the
BIST FIS Pattern Definition in any BIST FIS transmitted by the ICH8. This field is not
port specific — its contents will be used for any BIST FIS initiated on port 0, port 1,
port 2 or port 3. The specific bit definitions are:
Bit 7: T – Far End Transmit mode
Bit 6: A – Align Bypass mode
Bit 5: S – Bypass Scrambling
Bit 4: L – Far End Retimed Loopback
Bit 3: F – Far End Analog Loopback
Bit 2: P – Primitive bit for use with Transmit mode
Reserved
completion status from the device.
Description
SATA Controller Registers (D31:F2)
Intel
®
ICH8 Family Datasheet