NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 621

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EHCI Controller Registers (D29:F7, D26:F7)
15.2.3.1
Intel
®
ICH8 Family Datasheet
CNTL_STS—Control/Status Register
Offset:
Default Value:
27:17
15:12
9:7
Bit
31
30
29
28
16
11
10
6
Reserved
OWNER_CNT — R/W.
0 = Ownership of the debug port is NOT forced to the EHCI controller (Default)
1 = Ownership of the debug port is forced to the EHCI controller (i.e. immediately
Reserved
ENABLED_CNT — R/W.
0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the
1 = Debug port is enabled for operation. Software can directly set this bit if the port is
Reserved
DONE_STS — R/WC. Software can clear this by writing a 1 to it.
0 = Request Not complete
1 = Set by hardware to indicate that the request is complete.
LINK_ID_STS — RO. This field identifies the link interface.
0h = Hardwired. Indicates that it is a USB Debug Port.
Reserved. This bit returns 0 when read. Writes have no effect.
IN_USE_CNT — R/W. Set by software to indicate that the port is in use. Cleared by
software to indicate that the port is free and may be used by other software. This bit is
cleared after reset. (This bit has no affect on hardware.)
EXCEPTION_STS — RO. This field indicates the exception when the
ERROR_GOOD#_STS bit is set. This field should be ignored if the ERROR_GOOD#_STS
bit is 0.
000 =No Error. (Default)
001 =Transaction error: indicates the USB 2.0 transaction had an error (CRC, bad PID,
010 =Hardware error. Request was attempted (or in progress) when port was
All Other combinations are reserved
ERROR_GOOD#_STS — RO.
0 = Hardware clears this bit to 0 after the proper completion of a read or write.
1 = Error has occurred. Details on the nature of the error are provided in the Exception
taken away from the companion Classic USB Host controller) If the port was
already owned by the EHCI controller, then setting this bit has no effect. This bit
overrides all of the ownership-related bits in the standard EHCI registers.
same conditions where the Port Enable/Disable Change bit (in the PORTSC
register) is set. (Default)
already enabled in the associated PORTSC register (this is enforced by the
hardware).
(Default)
field.
Note: this should not be seen, since this field should only be checked if there is
an error.
timeout, etc.)
suspended or reset.
MEM_BASE + A0h
0000h
Description
Attribute:
Size:
R/W, R/WC, RO, WO
32 bits
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