NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 707

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express* Configuration Registers
18.1.16
18.1.17
Intel
®
ICH8 Family Datasheet
MBL—Memory Base and Limit Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 20h–23h
Default Value:
Accesses that are within the ranges specified in this register will be sent to the attached
device if CMD.MSE (D28:F0/F1/F2/F3/F4/F5:04:bit 1) is set. Accesses from the
attached device that are outside the ranges specified will be forwarded to the backbone
if CMD.BME (D28:F0/F1/F2/F3/F4/F5:04:bit 2) is set. The comparison performed is
MB ≥ AD[31:20] ≤ ML.
PMBL—Prefetchable Memory Base and Limit Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 24h–27h
Default Value:
Accesses that are within the ranges specified in this register will be sent to the device if
CMD.MSE (D28:F0/F1/F2/F3/F4/F5;04, bit 1) is set. Accesses from the device that are
outside the ranges specified will be forwarded to the backbone if CMD.BME (D28:F0/F1/
F2/F3/F4/F5;04, bit 2) is set. The comparison performed is PMBU32:PMB ≥
AD[63:32]:AD[31:20] ≤ PMLU32:PML.
31:20
19:16
31:20
19:16
15:4
15:4
3:0
3:0
Bit
Bit
Memory Limit (ML) — R/W. These bits are compared with bits 31:20 of the incoming
address to determine the upper 1-MB aligned value of the range.
Reserved
Memory Base (MB) — R/W. These bits are compared with bits 31:20 of the incoming
address to determine the lower 1-MB aligned value of the range.
Reserved
Prefetchable Memory Limit (PML) — R/W. These bits are compared with bits 31:20
of the incoming address to determine the upper 1-MB aligned value of the range.
64-bit Indicator (I64L) — RO. Indicates support for 64-bit addressing
Prefetchable Memory Base (PMB) — R/W. These bits are compared with bits 31:20
of the incoming address to determine the lower 1-MB aligned value of the range.
64-bit Indicator (I64B) — RO. Indicates support for 64-bit addressing
00000000h
00010001h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
32 bits
R/W, RO
32 bits
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