NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 850

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 173.
850
(Desktop
Only)
Sym
t301
t302
t303
t304
t305
t306
t307
t310
t311
t312
t313
Power Management Timings (Sheet 3 of 3)
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
28.992 µs to 32.044 µs.
The ICH8 STPCLK# assertion will trigger the processor to send a stop grant acknowledge
cycle. The timing for this cycle getting to the ICH8 is dependant on the processor and the
memory controller.
The ICH8 has no maximum timing requirement for this transition. It is up to the system
designer to determine if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control
the power planes.
If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5#
are asserted together similar to timing t287 (PCIRST# active to SLP_S3# active).
together, the delay from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as
much as 2.5 s.
This value is programmable in multiples of 1024 PCI CLKs. Maximum is 8192 PCI CLKs
(245.6 µs).
Assertion Width” and the “SLP_S4# Assertion Stretch Enable bits (D31:F0:A4h bits 5:3)”.
If the (G)MCH does not have the CPUSLP# signal, then the minimum value can be 0 µs.
This is non-zero to enforce the minimum assert time for DPRSLPVR. If the minimum assert
time for DPRSLPVR has been met, then this is permitted to be 0.
This is non-zero to enforce the minimum assert time for STP_CPU#. If the minimum assert
time for STP_CPU# has been met, then this is permitted to be 0.
This value should be at most a few clocks greater than the minimum.
When AMT enabled, S4_STATE# mimics SLP_S4# (Desktop Only).
These transitions are clocked off the internal RTC. 1 RTC clock is approximately from
These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns.
If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up
The Minimum/Maximum times depend on the programming of the “SLP_S4# Minimum
Note that this does not apply for synchronous SMIs.
This is a clock generator specification
CPUSLP# inactive to STPCLK# inactive
SLP_M# inactive to SLP_S3# inactive
SLP_S4# inactive to SLP_M# inactive
when AMT enabled
RSMRST# deassertion to LAN_RST#
deassertion
LAN Power Rails active to LAN_RST#
deassertion
LAN_RST# assertion to PWROK assertion
SLP_S3# active to Vcc supplies inactive
THRMTRIP# active to SLP_S3#,
SLP_S4#, SLP_S5# active
RSMRST# rising edge transition from
20% to 80%
RSMRST# falling edge transition
SLP_M# active to RSMRST# active
Parameter
Other Timings
Min
500
—
—
—
8
0
1
0
5
Max
±10
±10
50
—
—
—
—
—
3
PCI CLK
PCICLK
Intel
Units
Electrical Characteristics
ms
ms
ms
ns
ns
us
us
us
®
ICH8 Family Datasheet
Fig
41
42
27
34
Notes
24, 25
15
17
18
21
26