NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 350

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NH82801HBM S LB9A

Manufacturer Part Number
NH82801HBM S LB9A
Description
CONTROLLER HUB, ICH8M, I/O, 82801HBM
Manufacturer
Intel
Datasheet

Specifications of NH82801HBM S LB9A

Power Dissipation Pd
2.4W
Digital Ic Case Style
BGA
No. Of Pins
676
Pci Bus Type
I/O Controller Hub
Pci Express Base Spec
PCIe 1.1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
9.2.8
9.2.9
350
DMA Clear Byte Pointer Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
DMA Master Clear Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
7:0
Bit
7:0
Bit
Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the
I/O port address. Writing to this register initializes the byte pointer flip/flop to a known
state. It clears the internal latch used to address the upper or lower byte of the 16-bit
Address and Word Count Registers. The latch is also cleared by part reset and by the
Master Clear command. This command precedes the first access to a 16-bit DMA
controller register. The first access to a 16-bit register will then access the significant
byte, and the second access automatically accesses the most significant byte.
Master Clear — WO. No specific pattern. Enabled with a write to the port. This has the
same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer
flip/flop registers are cleared and the Mask Register is set.
Ch. #0
Ch. #4
xxxx xxxx
No
Ch. #0
Ch. #4
xxxx xxxx
3 = 0Ch;
7 = D8h
3 = 0Dh;
7 = DAh
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
WO
8-bit
Core
WO
8-bit
Intel
®
ICH8 Family Datasheet

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