NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 125

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.4.1.1
Table 42.
5.4.1.2
Table 43.
Intel
®
ICH8 Family Datasheet
LPC Cycle Types
The ICH8 implements all of the cycle types described in the Low Pin Count Interface
Specification, Revision 1.0.
LPC Cycle Types Supported
NOTES:
1.
2.
Start Field Definition
Start Field Bit Definitions
NOTE: All other encodings are RESERVED.
Bits[3:0]
Encoding
Bus Master Write
Bus Master Read
0000
0010
0011
1111
Cycle Type
DMA Write
DMA Read
I/O Write
I/O Read
For memory cycles below 16 MB that do not target enabled firmware hub ranges, the ICH8
performs standard LPC memory cycles. It only attempts 8-bit transfers. For larger
transfers, the ICH8 performs multiple 8-bit transfers. If the cycle is not claimed by any
peripheral, it is subsequently aborted, and the ICH8 returns a value of all 1s to the
processor. This is done to maintain compatibility with ISA memory cycles where pull-up
resistors would keep the bus high if no device responds.
Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer
can be to any address. However, the 2-byte transfer must be word-aligned (i.e., with an
address where A0=0). A dword transfer must be dword-aligned (i.e., with an address
where A1 and A0 are both 0).
Start of cycle for a generic target
Grant for bus master 0
Grant for bus master 1
Stop/Abort: End of a cycle for a
target.
1 byte only. Intel
multiple 8-bit transfers.
1 byte only. ICH8 breaks up 16- and 32-bit processor cycles into multiple
8-bit transfers.
Can be 1, or 2 bytes
Can be 1, or 2 bytes
Can be 1, 2, or 4 bytes. (See Note 2 below)
Can be 1, 2, or 4 bytes. (See Note 2 below)
Definition
Table 42
®
shows the cycle types supported by the ICH8.
ICH8 breaks up 16- and 32-bit processor cycles into
Comment
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