NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 444

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.1.22
444
BPS—Bridge Proprietary Status Register
(PCI-PCI—D30:F0)
Offset Address: 48h
Default Value:
31:17
15:7
Bit
6:4
3:2
1:0
Bit
16
2
1
0
Memory Read Multiple Prefetch Disable (MRMPD) — R/W.
0 = MRM commands will fetch multiple cache lines as defined by the prefetch
1 = Memory read multiple (MRM) commands will fetch only up to a single, 64-byte
Memory Read Line Prefetch Disable (MRLPD) — R/W.
0 = MRL commands will fetch multiple cache lines as defined by the prefetch algorithm.
1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned
Memory Read Prefetch Disable (MRPD) — R/W.
0 = MR commands will fetch up to a 64-byte aligned cache line.
1 = Memory read (MR) commands will fetch only a single DW.
Reserved
PERR# Assertion Detected (PAD) — R/WC. This bit is set by hardware whenever the
PERR# pin is asserted on the rising edge of PCI clock. This includes cases in which the
chipset is the agent driving PERR#. It remains asserted until cleared by software
writing a 1 to this location. When enabled by the PERR#-to-SERR# Enable bit (in the
Bridge Policy Configuration register), a 1 in this bit can generate an internal SERR# and
be a source for the NMI logic.
This bit can be used by software to determine the source of a system problem.
Reserved
Number of Pending Transactions (NPT) — RO. This read-only indicator tells debug
software how many transactions are in the pending queue. Possible values are:
000 = No pending transaction
001 = 1 pending transaction
010 = 2 pending transactions
011 = 3 pending transactions
100 = 4 pending transactions
101 = 5 pending transactions
110 - 111 = Reserved
NOTE: This field is not valid if DTC.MDT (offset 44h:bits 7:6) is any value other than
Reserved
Number of Active Transactions (NAT) — RO. This read-only indicator tells debug
software how many transactions are in the active queue. Possible values are:
00 = No active transactions
01 = 1 active transaction
10 = 2 active transactions
11 = Reserved
algorithm.
aligned cache line.
cache line.
‘00’.
00000000h
–
4Bh
Description
Description
Attribute:
Size:
PCI-to-PCI Bridge Registers (D30:F0)
R/WC, RO
32 bits
Intel
®
ICH8 Family Datasheet