NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 119

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.3.1.2.2
5.3.1.3
5.3.2
5.3.2.1
5.3.2.2
5.3.3
5.3.3.1
Intel
®
ICH8 Family Datasheet
64 Bytes
PCI requests are multiples of 64 bytes and aligned to make better use of memory
controller resources. Writes, however, can be on any boundary and can cross a 64 byte
alignment boundary
Configuration Request Retry Status
The LAN Controller might have a delay in initialization due to NVM read. If the NVM
configuration read operation is not completed and the device receives a Configuration
Request, the device will respond with a Configuration Request Retry Completion Status
to terminate the Request, and thus effectively stall the Configuration Request until such
time that the subsystem has completed local initialization and is ready to communicate
with the host.
Error Events and Error Reporting
Data Parity Error
The PCI Host bus does not provide parity protection, but it does forward parity errors
from bridges. The LAN Controller recognizes parity errors through the internal bus
interface and will set the Parity Error bit in PCI Configuration space. If parity errors are
enabled in configuration space, a system error will be indicated on the PCI Host bus to
the chipset. The offending cycle with a parity error will be dropped and not processed
by the LAN Controller.
Completion with Unsuccessful Completion Status
A completion with unsuccessful completion status (any status other than "000") will be
dropped and not processed by the LAN Controller. Furthermore, the request that
corresponds to the unsuccessful completion will not be retried. When this unsuccessful
completion status is received, the System Error bit in the PCI Configuration space will
be set. If the system errors are enabled in configuration space, a system error will be
indicated on the PCI Host bus to the chipset.
Ethernet Interface
The integrated LAN controller provides a complete CSMA/CD function supporting IEEE
802.3 (10Mb/s), 802.3u (100Mb/s) implementations. It also supports the IEEE 802.3z
and 802.3ab (1000Mb/s) implementations. The device performs all of the functions
required for transmission, reception and collision handling called out in the standards.
The mode used to communicate between the LAN controller and the LAN connect
device supports 10/100/1000 Mbps operation, with both half- and full-duplex operation
at 10/100 Mbps, and full-duplex operation at 1000 Mbps
MAC/LAN Connect Interface
The integrated LAN controller and LAN Connect Device communicate through either the
platform LAN connect interface (LCI) or GbE LAN connect interface (GLCI). All
controller configuration is performed using device control registers mapped into system
memory or I/O space. The LAN Connect Device is configured via the LCI or GbE Lan
connect interface.
The integrated MAC supports various modes as summarized in
Table
41.
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