NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 640

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.2.16
Note:
16.2.17
Note:
640
SLV_CMD—Slave Command Register (SMBUS—D31:F3)
Register Offset: SMBASE + 11h
Default Value:
This register is in the resume well and is reset by RSMRST#.
NOTIFY_DADDR—Notify Device Address Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 14h
Default Value:
This register is in the resume well and is reset by RSMRST#.
7:2
7:1
Bit
Bit
2
1
0
0
Reserved
SMBALERT_DIS — R/W.
0 = Allows the generation of the interrupt or SMI#.
1 = Software sets this bit to block the generation of the interrupt or SMI# due to the
HOST_NOTIFY_WKEN — R/W. Software sets this bit to 1 to enable the reception of a
Host Notify command as a wake event. When enabled this event is “OR”’d in with the
other SMBus wake events and is reflected in the SMB_WAK_STS bit of the General
Purpose Event 0 Status register.
0 = Disable
1 = Enable
HOST_NOTIFY_INTREN — R/W. Software sets this bit to 1 to enable the generation
of interrupt or SMI# when HOST_NOTIFY_STS (offset SMBASE + 10h, bit 0) is 1. This
enable does not affect the setting of the HOST_NOTIFY_STS bit. When the interrupt is
generated, either PIRQB# or SMI# is generated, depending on the value of the
SMB_SMI_EN bit (D31:F3:40h, bit 1). If the HOST_NOTIFY_STS bit is set when this bit
is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or
SMI#) is logically generated by AND’ing the STS and INTREN bits.
0 = Disable
1 = Enable
DEVICE_ADDRESS — RO. This field contains the 7-bit device address received during
the Host Notify protocol of the SMBus 2.0 Specification. Software should only consider
this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to
1.
Reserved
SMBALERT# source. This bit is logically inverted and ANDed with the
SMBALERT_STS bit (offset SMBASE + 00h, bit 5). The resulting signal is distributed
to the SMI# and/or interrupt generation logic. This bit does not effect the wake
logic.
00h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
SMBus Controller Registers (D31:F3)
R/W
8 bits
RO
8 bits
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ICH8 Family Datasheet